1. Field of Invention
The present invention relates to a method of fabricating a self-aligned contact (SAC). More particularly, the present invention relates to a method of fabricating a contact in an embedded dynamic random access memory (DRAM).
2. Description of Related Art
FIGS. 1A through 1B are schematic, cross-sectional views showing a conventional method of fabricating a self-aligned contact in an embedded DRAM. Referring to FIG. 1A, a semiconductor substrate 104 is provided. A shallow trench isolation (STI) structure 106 is formed on the substrate 104 to define a memory region 100 and a logic region 102 in an embedded dynamic random access memory (DRAM). The memory region 100 has an N-type metal oxide semiconductor (MOS) 108 and an N-type source/drain region 110 formed therein. The logic region 102 has an N/P-type MOS 112 having a dual gate structure and an N-type source/drain region 114 formed therein. A dielectric layer 116 is formed on the substrate 100 to cover the NMOS 108 and the N/PMOS 112. The dielectric layer 116 is patterned to form a contact hole in the memory region 100. The contact hole is filled with a conductive layer 118, which is composed of a polysilicon layer with doped N-type ions and a tungsten silicide layer. A portion of the conductive layer 118 extends to surface of the dielectric layer 116 neighboring the contact hole. Thus, the conductive layer 118 can be electrically coupled to the source/drain region 110.
Referring to FIG. 1B, an inter-layer electric (ILD) layer 120 is deposited over the substrate 104. Then, a planarization process is performed. Via holes are respectively formed in the memory region 100 and in the logic region 102 by photolithography and etching methods. The via holes are filled with a tungsten layer to respectively form vias 122a, 122b in the memory region 100 and in the logic region 102. Thus, the vias 122a, 122b can be electrically coupled to the conductive layer 118 in the contact hole and the source/drain regions 110.
While etching the inter-layer electric layer 120 to form the via 122a in the memory region 100 and the via 122b in the logic region 102, the tungsten layer of the conductive layer 118 and the silicon substrate 104 are respectively used as the etching stops. Due to the different etching stops and much different etching depths, alignment is difficult in the etching process, even when the etching stops are over-etched. The via 122b in the logic region 102 has larger aspect ratio because of the much deeper via 122b. Therefore, it is more difficult to align in the etching process.
In order to improve the alignment process mentioned above, a contact filled with a conductive layer of N-type doped polysilicon/tungsten silicide can be formed in the logic region 102 during alignment contact formation in the dielectric layer 116 in the memory region 100. The conductive layer in the logic region 102 is electrically coupled to the source/drain region 114. However, the MOS 112 in the logic region 102 has an N/P type dual gate structure, and a junction will be appear between the PMOS source/drain region 114 and the N-type conductive layer in the logic region 102. This is not the required electric connection. Therefore, the method is not used to solve the problem of the different depths while etching.
In addition, a method of forming a borderless contact is also used to overcome the difficulties of the different etching depths in the memory region and in the logic region due to the gradually reduced dimension of semiconductors. But it still has many problems, as shown as FIG. 2. FIG. 2 is a schematic, cross-sectional view showing a borderless contact. The distance between a MOS 202 and a STI structure 204 are much smaller to fit the design rule. A borderless contact 208 is formed in a dielectric layer 206. In order to reduce dimensions of devices, a portion of the borderless contact 208 is formed above the STI structure 204. Since the material of both the dielectric layer 206 and the STI structure 204 is oxide, it is difficult to stop on the substrate 200 while etching the dielectric layer 206 to form a contact hole 208, so that the substrate 200 is over-etched. An undesired trench 210 is formed in the substrate 200. Current leakage will occur while filling with a conductive layer in the later process.
FIG. 3 is a schematic, cross-sectional view showing a borderless contact. An oxide layer 304 and a silicon nitride layer 306 are sequentially formed over a MOS structure 302 on a substrate 300. A planarized dielectric layer 308 is formed over the substrate 300. A borderless contact hole 310 will be formed by photolithography and etching methods. While etching the dielectric layer 308, the silicon nitride layer 306 is first used as an etching stop. Then, the etched thickness of the oxide layer 304 is accurately controlled while etching the oxide layer 304. A source/drain region 312 beside the MOS 302 is completely exposed. Thus, a conductive layer formed subsequently can be easily coupled to a source/drain region 312 beside the MOS 302. However, the required etched depth of the contact hole 310 in the embedded DRAM is about 22000 .ANG.. Since the dielectric layer 308 is much thicker than the silicon nitride layer 306, the silicon nitride layer 306 is over-etched during the forming step of the contact hole 310. It causes the process in which the silicon nitride layer 306 is used as an etching stop to fail. If thickness of the silicon nitride layer 306 is increased, problems of stress will develop. Therefore, the borderless contact cannot achieve its efficacy in the above-mentioned conditions.